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A Sampling of Current and Past Projects
Some of the current and past projects developed by Seattle Semiconductor:
Project: Ganges
Project Type: Obsolescence/End Of Life remediation
Project Details: Involved translating an existing FPGA design into a ChipX Structured ASIC fabric; Included design documentation, verification environment development and synthesis of the Verilog to the ChipX structured ASIC libraries. Synthesis also included DFT insertion and scan chain stitching. Generated Constraint files for physical implementation.
Project: Pegasus
Project Type: BOM Cost Reduction
Project Details: Integration of multiple existing FPGA based IC's into a single, high performance structured ASIC Fabric. Project Included design documentation, Complete verification environment development (to emulate the entire system board), design migration into synthesizable Verilog from FPGA constructs, and synthesis of the Verilog to structured ASIC libraries. Synthesis also included DFT insertion and scan chain stitching. Generated Constraint files for physical implementation and provided post silicon validation.
Project: RedPill
Project Type: Digital IP Cleanup, remediation and optimization
Project Details: This is an ongoing project that involves a rewrite
and optimization of the customers ARM based digital IP (Excluding the processor core)and the full re-integration, verification, synthesis, DFT insertion and post silicon validation. With respect to size, this is about a 22M Gate project with an expected conclusion in June 2009.
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| Seattle Semiconductor, LLC. |
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| 206-769-9659 |
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