Project Feasibility and Analysis: Many companies, large or small, are unaware of the pitfalls of entering the digital IC realm. Generally senior management teams know that they can get significant cost savings, performance increases or preserve in-house IP by implementing a new idea or an existing design in an IC.

Seattle Semiconductor helps companies analyze whether an IC development effort is right for for a particular business, and if so, exactly which type of IC would be appropriate. Furthermore, Seattle Semiconductor can help set the expectations of cost and schedule before the project or idea gets into the budgetary and planning phase and can help perform the costed-BOM analysis to ensure that the end product meets the required goals, whatever those goals may be.

Project Management: Each project is assigned a project manager who will be responsible for all interfacing with the customer. The project manager may call in other engineering resources as is necessary but generally, the project manager is the focal point for all interaction with our customers. This provides a single point of contact to the customer and keeps confusion to a minimum.

All projects are defined and tracked using Microsoft Project. Each task that is involved in our customers project is identified and a resource assigned. This schedule is continuously updated and available to our customers at the weekly status project meeting.

Documentation: As has been stated before, Documentation is THE most critical piece of the design project and, as such, Seattle Semiconductor takes documentation very seriously. All documentation is performed using Microsoft Office tools. We do understand that some of our customers may have requirements for documentation in other formats and we will work with those customers to accommodate their needs, we initially create the documentation in Microft Office format for ease of use internal to Seattle Semiconductor. The list of documentation and the order in which it is provided is as follows: Statement of Work/Definition of Deliverables (SOW): _SOW.doc Analysis of Project: Cost and feasibility analysis.doc

• ASIC Requirements Document (ARD): _ARD.doc
• ASIC Architectural Analysis Document (AAD): _aad.doc
• ASIC Detailed Design Specification (ADD):_ADD.doc
• ASIC Design Verification Specification (AVS):_AVS.doc
• ASIC Tapeout Checklist (ATC):_ATC.doc
• ASIC Design Validation Specification:_Validation_Specification.doc
• ASIC Programmers Reference Manual (PRM):_PRM.doc

Design Implementation: Seattle Semiconductor is primarily a Cadence design house. The majority of our tools are Cadence software with the exception of FPGA synthesis (Synplicity) and mapping (Xilinx/Altera). At this time, all of our designs are implemented in Verilog HDL and simulated using the Cadence Incisive Unified Simulator (IUS or NCSim). That being said, we do have VHDL simulation capabilities so using customer developed IP that is implemented in VHDL is generally not a problem. Synthesis is performed using Cadence synthesis tools (Except where noted for FPGA designs). The tools are either Encounter RTL Compiler (RC) or an older but still perfectly capable Cadence tool known as BuildGates.

Design Verification: Design Verification is performed using the Cadence Incisive Simulator and the open source TestBuilder C++ verification libraries. Seattle Semiconductor has a significant amount of Verification IP built in the TestBuilder environment so we can often provide early looks at the verification task for each project.